一种应用于SRAM中的高速电压模型灵敏放大器

doi:10.3969/j.issn.0253-2778.2018.09.002

中国科学技术大学学报 ›› 2018, Vol. 48 ›› Issue (9): 696-702.DOI: 10.3969/j.issn.0253-2778.2018.09.002

一种应用于SRAM中的高速电压模型灵敏放大器

刘康生，虞致国*，王恬，梁思思，钱黎明，顾晓峰

1.江南大学电子工程系，江苏无锡 214122；2.中国电子科技集团公司第五十八研究所，江苏无锡 214035

收稿日期:2017-10-27 修回日期:2017-04-29 接受日期:2017-04-29 出版日期:2018-09-30 发布日期:2017-04-29

A high-speed voltage-mode sense amplifier for SRAM

LIU Kangsheng, YU Zhiguo*, WANG Tian, LIANG Sisi2, QIAN Liming2, GU Xiaofeng

Received:2017-10-27 Revised:2017-04-29 Accepted:2017-04-29 Online:2018-09-30 Published:2017-04-29
Contact: YU Zhiguo
About author:LIU Kangsheng, male, born in 1992, Master candidate. Research field: IC design and test. E-mail: 562490958@qq.com
Supported by:
Supported by Fundamental Research Funds for the Central Universities (JUSRP51510), Summit of the Six Top Talents Program of Jiangsu Province (2013-DZXX-027), Postgraduate Research & Practice Innovation Program of Jiangsu Province (KYLX16_0776, SJLX16_0500, SJCX17_0510), and China Scholarship Council(201706795031).

摘要/Abstract

摘要： 设计了一种应用于静态随机存储器（SRAM）读数据过程中的电压型灵敏放大器（SA）.与传统交叉耦合结构SA相比，增加了由NMOS管构成的第二级交叉放大电路及由上拉和下拉电路组成的输出电路.改进的结构能在快速而且高增益地放大位线上电压差的同时，改善灵敏度低的问题，确保了SRAM在不工作时数据输出端口的输出不受内部干扰.仿真结果表明，与传统结构相比，本设计减少了为确保输出节点全摆幅而所需的95%的位线上电压，同时在相同差分电压输入的情况下，响应时间减少了80%.

关键词: 灵敏放大器, 交叉耦合, 电压模型

Abstract: This paper reports a novel sense amplifier (SA) suitable for voltage sensing in the read operation of static random access memory (SRAM). Contrary to the conventional cross-coupled SA, an NMOS cross coupling amplifier is added as the second stage amplifier and the pull-up and pull-down circuits are added as the output circuit. The proposed structure can quickly amplify the bit line voltage difference with high gain, improve the sensitivity, and ensure that the data output port of the SRAM encounters no interference when the utility model is not working. The simulation results show that this design reduces 95% of the voltage required for the bit lines to guarantee the full swing at output nodes and shortens 80% of the sensing delay for the same input voltage difference compared with the conventional SA.

Key words: sense amplifier, cross-coupled, voltage-mode, high-speed

中图分类号:

TN722

刘康生，虞致国*，王恬，梁思思，钱黎明，顾晓峰. 一种应用于SRAM中的高速电压模型灵敏放大器[J]. 中国科学技术大学学报, 2018, 48(9): 696-702.

参考文献

［1］
CHRISANTHOPOULOS A, TSIATOUHAS Y, ARAPOYANNI A, et al. SRAM oriented memory sense amplifier design in 0.18 μm CMOS technology [C]// IEEE International Symposium on Circuits and Systems. Phoenix-Scottsdale, USA: IEEE Press, 2002: 145-148.
[2] WEN L, CHENG X, ZHOU K J, et al. Bit-Interleaving-enabled 8T SRAM with shared data-aware write and reference-based sense amplifier [J]. IEEE Transactions on Circuits & Systems II Express Briefs, 2016, 63(7): 643-647.
[3] PENG C Y, TAO Y, LU W, et al. A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier [J]. IEICE Electronics Express, 2015, 12(5): 20150102.
[4] MUKHOPADHYAY S, MAHMOODI H, Roy K. Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006, 24(12): 1859-1880.
[5] DO A T, KONG Z H, YEO K S, et al. Design and sensitivity analysis of a new current-mode sense amplifier for low-power SRAM [J]. IEEE Transactions on Very Large Scale Integration Systems, 2011, 19(2): 196-204.
[6] NOH K J, KIM J H, LEE C H, et al. A new dual asymmetric bit-line sense amplifier for low-voltage dynamic random access memory [J]. IEICE Electronics Express, 2013, 10(18): 20130647.
[7] UDDIN N, THIEDE A. Common gate cross-coupled differential amplifier for near-field sensors [J]. Electronics Letters, 2009, 45(18): 918-920.
[8] DO A T, LOW Y S J, KONG Z H, et al. A full current-mode sense amplifier for low-power SRAM applications[C]// IEEE Asia Pacific Conference on Circuits and Systems. Macao, China: IEEE Press, 2008: 1402-1405.
[9] ZHANG H. Design of a high speed sense amplifier circuit [J]. Microelectronics, 2015: 45(3): 294-297.
[10] LEE H, ALZATE J G, DORRANCE R, et al. Design of a fast and low-power sense amplifier and writing circuit for high-speed MRAM [J]. IEEE Transactions on Magnetics, 2015, 51(5): 1-7.
[11] GUNDU A K, HASHMI M S, GROVER A. A new sense amplifier topology with improved performance for high speed SRAM applications[C]// 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems. Kolkata, India: IEEE Press, 2016: 185-190.
[12] JEONG H, KIM T, KANG K, et al. Switching pMOS sense amplifier for high-density low-voltage single-ended SRAM [J]. IEEE Transactions on Circuits & Systems I Regular Papers, 2017, 62(6):1555-1563.
[13] CHOI W, PARK J S, KANG G. Dynamic stability estimation for latch-type voltage sense amplifier[C]// International SoC Design Conference. Jeju, South Korea: IEEE Press, 2014: 218-219.
[14] CHANG M F, SHEN S J, LIU C C, et al. An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory [C]// IEEE International Solid-state Circuits Conference. San Francisco, USA: IEEE Press, 2011: 206-208.
[15] LI Y, WEN L, ZHANG Y, et al. An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing [J]. IEICE Electronics Express, 2014, 11(3): 20130992.

()
()

一种应用于SRAM中的高速电压模型灵敏放大器

A high-speed voltage-mode sense amplifier for SRAM

PDF (PC)

可视化

摘要/Abstract

引用本文

使用本文

参考文献

相关文章 0

编辑推荐

Metrics

本文评价