Journal of University of Science and Technology of China ›› 2014, Vol. 44 ›› Issue (4): 310-316.DOI: 10.3969/j.issn.0253-2778.2014.04.008

• Original Paper • Previous Articles    

A multiprocessor architecture supporting dynamic partial reconfiguration

FENG Xiaojing, LI Xi, WANG Chao, CHEN Peng, ZHOU Xuehai   

  1. 1.School of Computer Science and Technology, USTC, Hefei 230027, China; 2.Embedded System Lab, Suzhou Institution for Advanced Study, USTC, Suzhou 215123, China
  • Received:2013-03-18 Revised:2013-07-16 Accepted:2013-07-16 Online:2013-07-16 Published:2013-07-16

Abstract: The intrinsic characteristics of embedded applications such as diversity and variability, together with their stringent requirements for computing performance, impose significant challenges on embedded system design. By providing a hardware/software co-design flow, an underlying communication interface, a parallel programming model and the relevant runtime environment, dynamic partial reconfigurable computing (DPR) technology was presented for service-oriented multiprocessor (SOMP) system. The DPR technology can effectively improve the system flexibility without performance loss, enabling the system to satisfy the requirements of more diverse embedded applications. An SOMP prototyping system has been implemented on the development board for the Xilinx Virtex-5 FPGA. A series of experiments were conducted and the results demonstrate the correctness and the resulting flexibility of the proposed architecture.

Key words: reconfigurable computing, dynamic partial reconfiguration (DPR), service-oriented architecture (SOA), heterogeneous multicore system

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