Journal of University of Science and Technology of China ›› 2015, Vol. 45 ›› Issue (7): 608-613.DOI: 10.3969/j.issn.0253-2778.2015.07.012

• Research Articles • Previous Articles    

An in-place FFT algorithm for high data parallelism architecture

  

  1. 1.School of Computer and Information, Hefei University of Technoogy, Hefei 230009, China;  2. No.38 Research Institude, China Electronics Technoogy Group Corporation, Hefei 230088, China;  3. School of Computer Science and Technology, University of Science and Technology of China, Hefei 230027, China
  • Online:2015-07-30 Published:2023-05-15

Abstract: The on-chip memory in DSP is small, and applications for DSP are often data-intensive, which requires that space complexity as well as time complexity must be considered when algorithms are designed. So a in-place bit reverse algorithm was proposed. Then, to take advantage of memory bandwidth offered by DSP, an effective in-place FFT algorithm with part bit reverse was designed and implemented on BWDSP. Experiment result shows that, compared with the out-of-place FFT algorithm, its space complexity is significantly reduced,while the loss of time efficiency for the proposed in-place FFT algorithm is acceptable.

Key words: bit reverse, inplace, FFT, space complexity, time complexity

CLC Number: