［1］
CHRISANTHOPOULOS A, TSIATOUHAS Y, ARAPOYANNI A, et al. SRAM oriented memory sense amplifier design in 0.18 μm CMOS technology [C]// IEEE International Symposium on Circuits and Systems. Phoenix-Scottsdale, USA: IEEE Press, 2002: 145-148.
[2] WEN L, CHENG X, ZHOU K J, et al. Bit-Interleaving-enabled 8T SRAM with shared data-aware write and reference-based sense amplifier [J]. IEEE Transactions on Circuits & Systems II Express Briefs, 2016, 63(7): 643-647.
[3] PENG C Y, TAO Y, LU W, et al. A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier [J]. IEICE Electronics Express, 2015, 12(5): 20150102.
[4] MUKHOPADHYAY S, MAHMOODI H, Roy K. Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006, 24(12): 1859-1880.
[5] DO A T, KONG Z H, YEO K S, et al. Design and sensitivity analysis of a new current-mode sense amplifier for low-power SRAM [J]. IEEE Transactions on Very Large Scale Integration Systems, 2011, 19(2): 196-204.
[6] NOH K J, KIM J H, LEE C H, et al. A new dual asymmetric bit-line sense amplifier for low-voltage dynamic random access memory [J]. IEICE Electronics Express, 2013, 10(18): 20130647.
[7] UDDIN N, THIEDE A. Common gate cross-coupled differential amplifier for near-field sensors [J]. Electronics Letters, 2009, 45(18): 918-920.
[8] DO A T, LOW Y S J, KONG Z H, et al. A full current-mode sense amplifier for low-power SRAM applications[C]// IEEE Asia Pacific Conference on Circuits and Systems. Macao, China: IEEE Press, 2008: 1402-1405.
[9] ZHANG H. Design of a high speed sense amplifier circuit [J]. Microelectronics, 2015: 45(3): 294-297.
[10] LEE H, ALZATE J G, DORRANCE R, et al. Design of a fast and low-power sense amplifier and writing circuit for high-speed MRAM [J]. IEEE Transactions on Magnetics, 2015, 51(5): 1-7.
[11] GUNDU A K, HASHMI M S, GROVER A. A new sense amplifier topology with improved performance for high speed SRAM applications[C]// 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems. Kolkata, India: IEEE Press, 2016: 185-190.
[12] JEONG H, KIM T, KANG K, et al. Switching pMOS sense amplifier for high-density low-voltage single-ended SRAM [J]. IEEE Transactions on Circuits & Systems I Regular Papers, 2017, 62(6):1555-1563.
[13] CHOI W, PARK J S, KANG G. Dynamic stability estimation for latch-type voltage sense amplifier[C]// International SoC Design Conference. Jeju, South Korea: IEEE Press, 2014: 218-219.
[14] CHANG M F, SHEN S J, LIU C C, et al. An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory [C]// IEEE International Solid-state Circuits Conference. San Francisco, USA: IEEE Press, 2011: 206-208.
[15] LI Y, WEN L, ZHANG Y, et al. An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing [J]. IEICE Electronics Express, 2014, 11(3): 20130992.
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